A CPU-FPGA heterogeneous platform-based monitoring system and redundant mechanisms

Abstract

This paper presents a practical view of how to implement a Dual Modular Redundancy (DMR) scheme in a CPU-FPGA (Central Processing Unit — Field-Programmable Gate Array) heterogeneous platform-based monitoring system, which is also described. FPGAs in a monitoring system can be valuable resources when it is important to either have a reprogrammable system or fast response/acquisition rates when processing large volumes of data. On the other side, CPUs are affordable options for most other processing tasks. A heterogeneous platform is proposed and aims to achieve a reliable, however cost-effective solution. After this, the paper will focus on matters such as synchronization between units, data redundancy and self-monitoring schemes. The implemented design was thoroughly tested, showing effectiveness in terms of redundancy with improved reliability.