Behavioural models for analog to digital conversion architectures for deep submicron technology nodes

Abstract

Non-idealities such as static device mismatch and dynamic timing mismatch, in different architectures of multi-steps analog to digital converter affect the redundancy and performance at the output of an instrument. Redundant sign digit (RSD) is an approach of calibration have been proposed to detect and automation no anymore only for cyclic converter but also for multistage A/D with M-bits per cycle for correction of errors in order to improve the resolution and the redundancy of A/D converters and to adapt the high performance of digital signal processing system. In this paper, we will presented a behavioral model in order to investigate the impact of different sources of error at different levels of simulation based at the comparison of RSD to conventional converter with Z extra decision level (CRZ).