Low power single bitline 6T SRAM cell with high read stability

Abstract

This paper presents a novel CMOS 6-transistor SRAM cell for different purposes including low power embedded SRAM applications and stand-alone SRAM applications. The data is retained by the cell with the help of leakage current and positive feedback, and does not use any refresh cycle. The size of the new cell is comparable to the conventional six-transistor cell of same technology and design rules. Also, the proposed cells uses a single bit-line for both read and write purposes.