A 3.5–9.5 GHz compact digital power amplifier with 39.3% peak PAE in 40nm CMOS technology

2015 IEEE International Wireless Symposium (IWS 2015) Pub Date : 2015-07-27 DOI:10.1109/IEEE-IWS.2015.7164565

H. Qian, J. Liang, Xun Luo

引用次数: 8

Abstract

A 3.5-9.5 GHz fully integrated digital power amplifier (DPA) with peak PAE of 39.3% in 40nm CMOS technology intended for a polar transmitter is presented. A compact wideband DPA design technique employing stacked stepped-impedance (SSI) transformer is firstly introduced to improve the power efficiency while tracking optimum load impedance in a wide bandwidth. This is the only reported wideband DPA operating above 3 GHz with a record fractional bandwidth (FBW) of 92.3%. The DPA exhibits peak output power of 22.2dBm and peak drain efficiency of 46.2% with 1.2V supply. The core chip size is only 0.22 mm2.

查看原文本刊更多论文

3.5-9.5 GHz紧凑型数字功率放大器，峰值PAE为39.3%，采用40nm CMOS技术

提出了一种采用40nm CMOS技术、峰值PAE为39.3%的3.5-9.5 GHz全集成数字功率放大器(DPA)。提出了一种采用叠置阶跃阻抗(SSI)变压器的紧凑型宽带DPA设计技术，以提高功率效率，同时在宽频带内跟踪最佳负载阻抗。这是唯一报道的工作在3ghz以上的宽带DPA，其记录分数带宽(FBW)为92.3%。在1.2V电源下，DPA的峰值输出功率为22.2dBm，峰值漏极效率为46.2%。核心芯片尺寸仅为0.22 mm2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2015 IEEE International Wireless Symposium (IWS 2015)

自引率

0.00%

发文量