Analysis of Transient Faults on a MIPS-Based Dual-Core Processor

Abstract

This paper presents a simulation-based fault injection analysis of a MIPS-based dual-core processor. In order to fulfill the requirement of this analysis, 114 different fault targets are used in various points of main components which are described in VHDL language; each experiment was repeated 50 times, resulting in 5700 transient faults in this simulation model. The experimental results demonstrate that, depending on the fault injection targets and the benchmark characteristics, fault effects vary significantly. On average, up to 35.2% of injected faults are recovered in simulation time, while 52.6% of faults lead to system failure, and the remaining 12.2%, treat as latent errors. Different benchmarks show different vulnerability for various components; but on average, Arbiter and Message passing interface are the most vulnerable components outside the tiles, while PC and Bus Handler have highest failure rate among in-tile components. Fault injection on each region has noticeable impact on the result of the other core. In general, fault injection in Shared regions has highest contribution in system failure.