A 12-bit SAR ADC in 180 nm Technology for Smart Sensor Systems

Adrian Hofmann, Andreas Käberlein, Elias Kögel, Marco Ramsbeck, J. Horstmann
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引用次数: 1

Abstract

High-level models serve their purpose for a time- and memory-efficient abstraction of the implementation and functionality of integrated circuits, but often experience high distinction between the transistor-level simulation and measurements. A 12-bit SAR ADC is designed as a high-level model as well as a transistor-level implementation in a 0.18 μm technology for smart sensor system applications. An accurate high-level model is developed and compared to actual transistor-level simulations as well as measurement results of the manufactured chip. Crucial design steps are shown to accurately design the high-level model and achieve a model that closely follows the behavior of the manufactured circuit, which can be used to highly accelerate the design process of smart sensor systems
用于智能传感器系统的180nm技术的12位SAR ADC
高级模型的目的是对集成电路的实现和功能进行时间和内存效率的抽象,但通常在晶体管级模拟和测量之间存在很大的区别。12位SAR ADC设计为高级模型,并采用0.18 μm技术实现晶体管级,适用于智能传感器系统应用。建立了精确的高阶模型,并与实际的晶体管级仿真和制造芯片的测量结果进行了比较。给出了精确设计高级模型的关键设计步骤,并实现了与制造电路行为密切相关的模型,可用于大大加快智能传感器系统的设计过程
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