Experiences and issues in VHDL-based synthesis

Abstract

Synthesis systems that take VHSIC hardware description language (VHDL) as input are now widespread, and impose certain constraints, or conditions of usage, on the designer, most of which help to achieve a fast turnaround. The authors report experiences with using VHDL-based synthesis in a design environment where delivering workable circuits in short schedules is of paramount importance. Results show that a fully automated hardware description language (HDL)-based solution is not possible with present synthesis technology; designer intervention is almost always required.<>