Chip-independent Error Correction in main memories

Abstract

Main memory reliability is an important concern in today's computer systems. Error Correction Codes (ECCs) improve memory reliability but have high area and energy overheads. Furthermore, ECCs cannot be easily applied to memories with wide chips such as stacked memories. In this paper, we introduce a new low-overhead error correction scheme, which can easily be applied to DRAM memories with wide devices. The scheme is called Chip-Independent Error Correction (CIEC) because it is independent of the memory chip width. Our simulation results in the context of transient faults show that CIEC has only 4.5% energy overhead, 0.5% performance overhead, and 0.7% area overhead on the processor chip as compared to a non-ECC DIMM while its reliability is much higher than the reliability of non-ECC DIMMs.