High Speed Multi-channel Data Cache Design Based on DDR3 SDRAM

Abstract

With the rapid development of microelectronics technology, the amount of data information is becoming larger and larger, and the speed of data processing is becoming higher and higher. In order to meet the needs of today's data cache and solve a series of problems such as unstable data transmission and data loss caused by the common data cache technology due to its small capacity and slow data processing speed, a synchronous dynamic random access memory (DDR3 SDRAM) based data cache design method with high speed and large capacity and multi-channel is proposed to achieve fast and efficient real-time storage of eight-channel video data. Based on Vivado MIG IP core and Kintex-7 FPGA as the control core, asynchronous FIFO with read/write bit width ratio of 8:1 is realized, and the read/write cache control module is designed, and the real-time data is finally cached to the corresponding address of DDR3 SDRAM. Improved DDR3 SDRAM bandwidth utilization. The experimental results show that the system can access 8-channel high speed video data, and the data transmission is stable and reliable. The design is mainly composed of multi-channel data acquisition module, cross-clock domain data processing module, read and write priority arbitration and other modules, with a working frequency of up to 400M Hz. It has been verified that the design can be used for real-time acquisition system of space-borne video storage.