Dynamic FET stack control for enhanced efficiency in envelope tracking power amplifiers

Abstract

In this work, a dynamic FET stacking is proposed to implement an envelope tracking power amplifier (ET PA) to enhance the efficiency at low VDD and backed-off power range. Quadruple-stacked CMOS power cell is reconfigured to operate as quasi-triple or quasi-double stacks according to the magnitude of the input envelope. The overall ET PA with the proposed RF power amplifier and envelope amplifier fabricated using 0.18-μm SOI CMOS shows an overall efficiency of 46% for 10 MHz LTE and 52% for WCDMA signal, which are 4.5% and 2.8% higher than the static stack ET PA. Adequate linearity has also been demonstrated using the gain and phase step compensation circuitry.