Stage-based Path Delay Prediction with Customized Machine Learning Technique

Abstract

Static timing analysis is an important timing analysis technique in the physical design process of integrated circuits, facing the challenge of speed and accuracy trade-off in advanced nodes. Expensive and burdensome path-based analysis (PBA) forces designers to adopt faster graph-based analysis (GBA) in more early flows at the cost of pessimism. Existing work focuses on reducing pessimism but ignores the degree of optimism. In this paper, we propose a stage-based delay model based on machine learning technique with customized loss function to rapidly generate predicted PBA timing results from the pessimistic GBA timing report with considering the asymmetric loss. The model could also enable the designers to identify the false violation path in GBA report with less time cost to reduce the over-design and margin in post-route optimization phase. Experimental results demonstrate that the mean absolute error of predicted PBA slack divergence reduces 66.7%~79.8% compared to GBA-PBA slack divergence (from 17.79ps to 5.92ps and 3.6ps) with about 3X runtime overhead reduction on a 28nm industrial ASIC for each corner. It can also correct about 75.6% false violation paths in GBA timing report.