Implementation of optimal multi-rate cardiac signal processing on a 1967BH028 DSP from “Milandr” design center in order to analyze heart rate variability

Abstract

The analysis of heart rate variability in recent years has become very widespread as a tool for versatile diagnostics of the functional state of the human body. The analysis of heart rate variability is associated with processing procedures characterized by high requirements for the speed of the computational element base. These procedures, however, must be performed in real time in an embedded computing system. The article deals with the problem of reducing the number of computational operations and an implementation of heart rate variability on modern processor elements offered by the domestic industry. The aim of the work is to model the optimal structure of multi-rate signal processing in the analysis of heart rate variability and to implement this structure on a digital signal processor with an estimate of processing time and `memory costs. By modeling, it is shown that the developed optimal structure of multi-rate processing allows getting a reliable processing result while reducing computational costs by several hundred thousand times compared to the implementation at the original sampling frequency. The optimal structure is constructed as a two-stage filtering-decimation structure, followed by passing the signal at a reduced sampling rate through a set of analysis filters. The end-to-end decimation factor is 500. The simulation results allow us to proceed to the implementation on the signal processor. The program codes of the main processing stages, including filtration and filtration decimation, have been developed. It is shown that the processing time with high-quality optimization of program codes can reach 10 million clock cycles, which corresponds to 23 ms and fully satisfies the real-time processing requirement, leaving a large margin for implementing additional more complex analysis algorithms on the same processor. The practical significance of the results is that in addition to the proposed method of reducing computational and memory costs, a prototype of a possible device based on one of the most popular domestic signal processors is obtained.