{"title":"Reconfigurable processor for public-key cryptography","authors":"N. Symth, M. McLoone, J. McCanny","doi":"10.1109/SIPS.2005.1579848","DOIUrl":null,"url":null,"abstract":"This paper proposes a novel processor architecture that provides a reconfigurable computing platform for modular exponentiation used in RSA and Diffle-Hellman public-key cryptography. The processor can operate autonomously to perform all operations required for modular exponentiation. A parallel-processing pipeline offers the versatility to perform any large-integer arithmetic. The processor can perform modular exponentiation using classical exponentiation, Montgomery multiplication and Barrett reduction. Hardware exponent receding is used to improve the efficiency of square-and-multiply algorithms by 15%. The performance of the processor is competitive in comparison to fixed functionality hardware implementations and is significantly faster than general purpose public-key cryptographic processors previously reported in the literature.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2005.1579848","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper proposes a novel processor architecture that provides a reconfigurable computing platform for modular exponentiation used in RSA and Diffle-Hellman public-key cryptography. The processor can operate autonomously to perform all operations required for modular exponentiation. A parallel-processing pipeline offers the versatility to perform any large-integer arithmetic. The processor can perform modular exponentiation using classical exponentiation, Montgomery multiplication and Barrett reduction. Hardware exponent receding is used to improve the efficiency of square-and-multiply algorithms by 15%. The performance of the processor is competitive in comparison to fixed functionality hardware implementations and is significantly faster than general purpose public-key cryptographic processors previously reported in the literature.