{"title":"Low Power Swing Restoration Circuit Reduce Threshold Voltages of SRAMs Improve Read and Write Operations","authors":"Vinod Kumar, Ram Murti Rawat","doi":"10.1109/iSES52644.2021.00018","DOIUrl":null,"url":null,"abstract":"In this paper Swing restoring inverter (SRI), a fast speed and low power circuit technology for VLSI applications that is discussed. In this technology, high speed low power SRAMs circuit performance is achieved by using an SRI to execute threshold voltage reductions and a swing restoring circuit of the latch kind to drive dual node voltages. Cadence Virtuoso schematics tool was used to design an SRI-based SRAM circuit with 130 nm technology for very high speed, low-power VLSI applications. This Paper is organized as follows: - I. Introduction II. Related work III. The proposed work IV. Results and discussion and V. Conclusion.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/iSES52644.2021.00018","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper Swing restoring inverter (SRI), a fast speed and low power circuit technology for VLSI applications that is discussed. In this technology, high speed low power SRAMs circuit performance is achieved by using an SRI to execute threshold voltage reductions and a swing restoring circuit of the latch kind to drive dual node voltages. Cadence Virtuoso schematics tool was used to design an SRI-based SRAM circuit with 130 nm technology for very high speed, low-power VLSI applications. This Paper is organized as follows: - I. Introduction II. Related work III. The proposed work IV. Results and discussion and V. Conclusion.