Design and Analysis of Booth Multiplier with Optimised Power Delay Product

Abstract

In most of the VLSI systems, multiplier being the vital part consumes nearly 15-20% of total IC power and is quiet slow in overall operation of the system. Thus it is essential to have an efficient design for the multipliers to improve the overall performance of the system. Booth multiplier reduces the number of partial products, taking into account two bits of the multiplier at a time, resulting in speed advantage over other multiplier architectures. With this advantage, Booth Multiplier is widely used in multiplication process for various digital and DSP circuits. The objective of this paper is to implement an optimized Booth Multiplier (8*8) with improved Power consumption and Delay Product (PDP). The sign extension is implemented using a single inverter and the addition operation is implemented by using custom designed Carry Skip Adders with IOT Full Adder. The design implementation and the simulations are done in Cadence Virtuoso V13.0 under 45nm technology.