A Novel Design of All Digital Phase Locked Loop for Wireless Applications

Abstract

This work presented simulation, synthesis and implementation of the PLL for communication system. The requirement of all digital phase lock loop has needed basically because the microprocessor don't have sufficient procession power at such elevated frequency still though integrated digitals to analog converter and analog to digitals converter. In this work effect of execution all digitals phase lock loop (ADPLL) is described for their application. The power, area and delay of the synthesizer have been analyzed. The results of the proposed synthesizer have been simulated and synthesized by Xilinx and same results have been implemented on FPGA. Future, other parameters can be analyzed and implemented using Vivado Xilinx.