Design and Simulation of a Capless Low Drop Out Voltage Regulator

2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT) Pub Date : 2018-12-01 DOI:10.1109/ICEECCOT43722.2018.9001436

Sujatha Kotabagi, Gautami Karkun, P. S. Bhat

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Abstract

The changing requirements of the industry is directing towards the full integration of SoC. This requires the power management block to have the Low Drop Out(LDO) regulator with reduced external capacitor. This paper proposes the study of behavior of the LDO voltage regulator with an external capacitor and capless low drop out voltage regulator. The regulated voltage of 1.8V is obtained using the typical power supply of 2.2V. The total quiescent current used in the circuit is less than 30uA with the load current variation of 0 to 20mA. The capless LDO architecture is verified in the UMC 180nm technology. The architecture provides a stable regulated voltage of 1.8V with both line and load variations and also for the transient variations. The stability issues are overcome using the compensation techniques which uses a current amplifier and a capacitor in the differentiator configuration. The current amplifier implemented uses current mirror with current copying ratio of unity.

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无盖低降稳压器的设计与仿真

行业不断变化的需求正朝着SoC的完全集成方向发展。这要求电源管理模块具有具有减小外部电容的低降差(LDO)稳压器。本文提出了一种具有外置电容和无盖低差稳压器的LDO稳压器的性能研究。使用2.2V的典型电源获得1.8V的稳压电压。电路中使用的总静态电流小于30uA，负载电流变化范围为0 ~ 20mA。无帽LDO架构在联华电子180nm技术中得到验证。该体系结构提供1.8V稳定的稳压电压，包括线路和负载变化以及瞬态变化。使用补偿技术克服了稳定性问题，补偿技术在微分器配置中使用电流放大器和电容器。所实现的电流放大器采用电流镜，电流拷贝比为1。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT)

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