Analysis and minimization of short-circuit current in mesh clock network

Abstract

Mesh clock network is very effective at reducing clock skew. But mesh causes a large increase of power consumption, in particular due to shorted buffers. We first analyze the short-circuit power consumption of the mesh clock network. It is observed that skew distribution of premesh tree is important in determining the amount of short-circuit power. We then propose a new clock buffer, which practically eliminates short-circuit current in a mesh network. Experiments on a few test circuits using 40-nm technology indicate that clock power consumption is reduced by 13.0% on average with 4.8% of area increase; this can be compared to buffer sizing, which only achieves 5.6% saving of power.