Analysis of Interface Trap Charges on Dielectric Pocket SOI-TFET

Abstract

In this brief, the reliability of SOI-TFET with dielectric pocket (DP SOI-TFET) has been investigated in the presence of fixed trap charges at the interface between dielectric pocket (DP) and drain region. During numerical simulation, both types of trap charges like donor (i.e. positive) and acceptor (i.e. negative) have been considered to analyse the impact on the performance of SOI-TFET having DP in drain region used for reduction of ambipolar conduction. We have compared the device performances such as ambipolar conduction, and OFF-state current of conventional SOI-TFET with both low and high- $\pmb{k}$ DP SOI-TFET in the presence of interface trap charges (ITCs). It has been found that SOI-TFET is more immune to interface trap charges when high- $\pmb{k}$ material is used as DP compared to low- $\pmb{k}$. Since, high- $\pmb{k}$ provides even more reduction in ambipolar conduction as compared to low- $\pmb{k}$, it can be preferred to be used a dielectric pocket in SOI-TFET.