On Optimization of Manufacturing of Bipolar Heterotransistors Framework Circuit of a High-voltage Element or to Increase Their Integration Rate: On Influence Mismatch-induced Stress

Abstract

In this paper, we introduce an approach to decrease dimensions of bipolar heterotransistors framework a circuit of a voltage divider biasing common emitter amplifier. Framework of the approach, we consider manufacturing of the divider in heterostructure with specific configuration. Several specific areas of the heterostructure should be doped by diffusion or by ion implantation. After this doping, dopant and/or radiation defects should be annealed by using optimized scheme. We also consider an approach to decrease value of mismatch-induced stress in the considered heterostructure. To make prognosis of technological process and obtain recommendations to optimize the process, we introduce an analytical approach to analyze mass and heat transport in heterostructures with account mismatch-induced stress.