Testing and Formal Verification of Decoder Circuit

Indu Bhuria, P. Inaniya, P. Kaler
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Abstract

Testing of 2-to-4 decoder circuit are been done using tetraMAX. It is observed that 54 possible stuck-at faults can be there in the 2-to-4 decoder circuit, tetraMAX ATPG can provide test coverage of 100 % Using design compiler. db file is generated which is used for functional verification of the design with respect to RTL design. Compare points are shown by cone views of the design.
解码器电路的测试与形式化验证
利用tetraMAX对2- 4解码器电路进行了测试。观察到在2对4解码器电路中可能存在54个卡滞故障,使用设计编译器,tetraMAX ATPG可以提供100%的测试覆盖率。该文件用于对RTL设计进行功能验证。比较点由设计的圆锥视图表示。
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