Power Side Channel Attack of AES FPGA Implementation with Experimental Results using Full Keys

Abstract

The ability to attack Advanced Encryption Standard (AES) algorithms in the last round has been shown to be possible by enumerating the key guesses one byte at a time. However, attacking the first round does not lend itself to such a technique because of the presence of the mix-column layer. We demonstrate an attack on the 1st round of AES encryption by defining a leakage function based on the full key, and then we apply correlation power analysis to successfully uncover the encryption key. The success rate, defined by the Euclidian distance fluctuation is 0.788, which is higher than similar applications in the current literature. We also introduce the concept of Kullback-Leibler entropy as a distinguisher for discriminating between the power measurements and the estimated power of the key guesses. We demonstrate this as a new way of reducing the key search space via key ranking with applications for power side-channel attacks on the implementations of AES algorithms in an FPGA.