Dynamic capacity modeling with multiple re-entrant workflows in semiconductor assembly manufacturing

Abstract

It is very challenging to gain competitive advantages in Flash assembly manufacturing mainly due to: widely and quickly fluctuating customer requests; with complicated workflows; and co-existence of new technology/equipment and legacy ones. In later 2003, Intel experienced capacity degradation mainly due to the introduction of multiple-chip products (MCP) with re-entrant workflows. We timely re-engineered our factory and generated new methodologies to achieve breakthrough operational excellence. We extended theory of constraints (TOC) to solve the problem of multiple bottlenecks, and developed the dynamic capacity model that captures variability of re-entrant manufacturing systems. Protective capacity (PC) and other parameters at constrained and near-constrained stations are regularly tracked and adjusted to accurately reflect line execution variability in terms of equipment, staff, and WIP. With the implementation and continuous improvement of these methodologies, we increase the factory output by 200% without major capital investment (avoiding millions of capital spending), we maintain 100% volume pass and line item pass for 41 weeks and still counting, and we achieve 30% unit cost cut and brought down subcon price by 26%, which results in over a dozen of millions of dollar cash saving for Intel.