Parallelization and performance prediction for HEVC UHD real-time software decoding

Abstract

In this paper, we present a parallelized HEVC decoder by restructuring the reference HEVC decoder, HM, as a task graph with LCU level granularity. Since the task graph reveals the potential parallelism of the algorithm explicitly, we are able to explore the wide design space of parallelization efficiently. Moreover, we propose an analytical method to estimate the throughput performance of the HEVC decoder after parallelization. The proposed method accurately predicts the decoding performance considering sophisticated parallelization techniques, based on which we obtain the required number of cores in a multi-core processor for real-time UHD resolution decoding. Through experiments, we verify the performance increase by the proposed parallelization technique and the accuracy of the performance analysis method.