Speculative Read Write Locks

Abstract

Hardware Transactional Memory (HTM) has recently entered the realm of mainstream computing thanks to its integration in processors commercialized by major industrial manufacturers. HTM provides highly-efficient, hardware-assisted synchronization mechanisms for concurrent programs. Unfortunately, though, existing HTM implementations also suffer from severe limitations that are inherently related to their best-effort, hardware-based design. This work introduces SpRWL (Speculative Read Write Lock), a HTM-based implementation of read-write locks that provides a key benefit: allowing readers to execute outside the scope of hardware transactions, thus, effectively sparing them from any HTM-related limitation. SpRWL is the first HTM-based read-write lock implementation to support the concurrent execution of uninstrumented readers, while assuming a standard transaction demarcation API that is universally supported by any HTM implementation. Via an extensive experimental study, we show that SpRWL can achieve striking performance gains (up to 16x) with respect to state of the art read-write lock implementations based not only on pessimistic/lock-based schemes, but also on HTM-based techniques that exploit specific hardware mechanisms currently supported solely by a restricted number of architectures.