Design considerations for a 25-nanosecond tunnel diode memory

Abstract

About two years ago a tunnel diode memory system was described which employed substantially different techniques than those previously used. Although earlier systems had tended towards array arrangements that had the storage cells connected in parallel on one or more axes, the new system employed series connections along two axes. This new arrangement has several design and performance advantages compared to previous systems. The original paper described the basic approach and some of the earlier work which included the design of array cross sections and the associated driving and sensing circuits. Since that time one version of the system has been operational in two IBM 7030 systems, and a 16-word, fully-populated, higher-speed laboratory model was built and reported. The present paper describes the engineering considerations used in the design of a larger and faster memory employing the basic techniques.