JOGM: A CMOS cell layout style using jogged transistor gates

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410635

Ronald D. Hindmarsh

引用次数: 2

Abstract

A new width minimizing layout style called jogged gate matrix (JOGM) for CMOS cells is described. The traditional gate matrix layout style is modified by inserting 45/spl deg/ jogs into transistor gates. Thus, JOGM improves CMOS cell width by 23% to 31% in comparison to traditional gate matrix layout. An approach for automatic layout generation is suggested.<>

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JOGM:一种使用慢跑晶体管栅极的CMOS单元布局样式

描述了一种新的宽度最小化布局样式，称为慢跑门矩阵(JOGM)的CMOS电池。传统的栅极矩阵布局方式通过在晶体管栅极中插入45/spl°/ jogs来改进。因此，与传统栅极矩阵布局相比，JOGM将CMOS单元宽度提高了23%至31%。提出了一种自动生成布局的方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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