29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS

Abstract

Serial link transceivers that can operate across a wide range of data rates offer flexibility and rapid realization of single-chip multi-standard solutions. The ability to independently control the data rate of each lane in a multi-lane transceiver with fine granularity is also valuable [1,2]. The implementation of such transceivers would require analog front-ends and clocking circuits that can operate over a wide range of frequencies. As a result, compared to transceivers that are optimized to operate at one single data rate, flexible-rate transceivers are power and area hungry [1]. Because a single PLL cannot generate clocks across the entire interface operating range, [1,2] use multiple LC tanks, carefully optimized waveform shaping circuits, power hungry clock distribution, and complex frequency planning methods.