Performance Verification of Circuits

Abstract

This paper describes a multi-level simulation strategy for verifying and optimizing VLSI circuit performance. Circuit simulation alone is insufficient for ensuring that VLSI designs meet performance targets. To meet VLSI needs, a tri-level family of simulation tools consisting of critical path analyzers, parasitic timing simulators, and circuit simulators is proposed. The relationship and interface between these tools, including how they combine "tops-down" and "bottoms-up" design methodologies, and some results from the initial implementation of this strategy in actual VLSI product designs are also discussed.