A 6.3-8.7 GHz Phase-Locked Loop in 65nm CMOS

Abstract

This paper presents a fully-integrated charge-pump phase-locked loop (CPPLL) for 5G applications. The PLL is composed of a phase and frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO) and a programmable divider. To achieve low phase noise, the VCO employs class-C topology. Implemented in 65-nm CMOS, the PLL measures an output frequency range from 6.3 to 8.7 GHz, with phase noise of -122.9 dBc/Hz and -116.6 dBc/Hz @1MHz offset, respectively. The PLL consumes 50 mW and occupies a core area of 0.8 mm × 0.9 mm excluding the pads.