A New Fault Tolerant Method for Cascaded H-Bridge Inverters Based On Peak Reduction Post-Fault Control Method

Abstract

In This paper, a new post-fault control method for symmetric cascaded H-bridge multilevel inverters (CHB-MLIs) is proposed with the aim of the development of CHB-MLIs performance under faulty conditions due to decrease in common mode voltage (CMV). In other words, this technique addresses the exclusive process to select the optimal post-fault state among all available states possess the same amplitude of the output line to line voltages. As a result, this process leads to provide computed phase voltages references to apply to PWM block. Hence, this technique leads to decrease the common mode voltage and eliminate it under some desired output line-line voltages. Finally, the feasibility of the new technique is verified by MATLAB/SIMULINK for various faulty operating states.