High performance and area efficient Signed Baugh-Wooley multiplier with Wallace tree using compressors

Abstract

Signed Baugh-Wooley multiplier is famous for multiplication of signed multiplicands in twos complement data representation. In this Paper, a novel 4∶2 and 5∶2 compressors architecture is proposed. Wallace tree architecture is chosen to reduce the number of stages and by using the proposed compressors additional reduction of latency and area is achieved. The performance of these compressors is evaluated by including those in signed Baugh-Wooley multipliers with Wallace tree. The result shows 6.77 percentage reduction in cell area and 7.04 percentage faster than existing Signed Baugh-Wooley multiplier when 5∶2 compressor architecture is used.