Thermal variance-aware application mapping for mesh based network-on-chip design using Kernighan-Lin partitioning

Abstract

This paper presents a Kernighan-Lin bi-partitioning based approach to perform mapping the core graph of an application onto a mesh-based Network-on-Chip (NoC) architecture. It aims at optimizing both communication cost and thermal variance of the resulting solution. Experimental results show that the approach could obtain significant reduction in mean temperature of the die and its standard deviation, compared to many of the recently reported application mapping strategies such as NMAP [1], LMAP [2] and DPSO [3]. All these reported approaches attempt to obtained a communication aware mapping, without any concern about temperature profile of the die. Our proposed approach outperforms all these reported approaches except DPSO, in-terms of communication cost, whereas, in-terms of temperature profile, it outperforms all these approaches. Tradeoff between the communication cost and temperature profile could also be achieved.