An experiment in applying knowledge-based software engineering technology

Abstract

Presents the results of an experiment at applying knowledge-based software engineering technology to hardware/software co-design. The Reacto verification system, developed by the Kestrel Institute, was used to create a high-level, formal-based interface to VHDL which can effectively model both hardware and software design components. In addition to the theorem proving and simulation capabilities already provided to Reacto, extensions were made to incorporate time constraints, and compiler-based language mappings for generating VHDL from Reacto specifications were defined. Our experimental results clearly indicated the complimentary nature and benefits of developing high-level, formally defined interfaces between languages like Reacto and VHDL.<>