Impact of variation in gate line spacing and active layer thickness on performance of organic static induction transistor

Abstract

This research paper emphasizes on the impact of variation in gate line spacing (SG) and organic semiconductor (OSC) layer thickness on performance of pentacene based organic static induction transistor (OSIT). Furthermore, complete analysis along with performance parameters extraction is carried out using Atlas 2-D numerical device simulator. Effect of variation in gate line spacing (SG) is analyzed by varying SG of device. Besides this, effect of variation in OSC layer thickness is analyzed of OSIT device. This analysis shows that current conduction can be controlled effectively with smaller gate line spacing due to better coverage of channel region by depletion layer in off state. Analysis of variation in OSC layer thickness demonstrates that smaller reduction in OSC layer, have large improvement in Ion/Ioff ratio. Therefore, drive current of an OSIT can be controlled at optimum thickness of OSC layer.