A High-Resolution High-Linearity Three-Step Hybrid Time-to-Digital Converter in 40-nm CMOS

Abstract

In this paper, a high-resolution high-linearity three-step TDC design in 40-nm CMOS technology is presented. The coarse step was designed based on a counter to achieve a wide range. The medium step was designed based on a multi-phase clock interpolation structure with DLL to improve the linearity. The fine step was designed based on a vernier structure with ring oscillators to achieve high resolution. The simulation results show that the design has a 5-ps resolution and a 2-μs range. The DNL is in (−0.2, 0.65) LSB, and the INL is in (−0.9, 0.38) LSB.