BPGen: Functional verification of branch misprediction recovery logic via ADL

Abstract

Branch misprediction logic is very important in microprocessor control logic design. This paper presents a method for functional verification of branch misprediction recovery logic, named BPGen, which uses ADL (architecture description language) to describe the system architecture of microprocessor, defines fault model and instruction classification for branch misprediction logic, and generates the test programs automatically. The experiment result showed that the BPGen tool could complete the branch misprediction verification within an acceptable time, detected all the 23 bugs in an actual design project, and detected all the 38 design errors generated by the popular mutation technology.