High Performance and Energy Efficient Computing with Advanced SoIC™ Scaling

Abstract

High Performance Computing (HPC) system integration has gained significant growth momentum with ever-increasing demands on data transfer bandwidth and computing performance in support of data center and high-end server for 5G and AI applications. Advanced AI computing system with a high energy efficient performance (EEP) and a wide interconnect bandwidth is highly desirable. Moore’s Law continues to push transistor scaling to improve power consumption and computing performance with both architecture and materials innovations. To sustain cost and performance benefits with economics of scale, semiconductor technology innovations have been accelerated from system scaling perspective, leveraging chiplets partition and 2D/3D reintegration, by enabling ultra-fine pitch 3DIC inter-chip stack.3DFabric™ system integration platform provides a full spectrum of advanced system integration technologies including 3DIC stacking (aka SoIC™), advanced packaging technologies (aka CoWoS and InFO) with advanced wafer node technology to unlock customer innovations for the next generation HPC. System on Integrated Chips (SoIC™) is a fronted-end 3D inter-chip stacking technology to achieve high interconnect density and high bandwidth with high energy efficiency. Scaling down in the SoIC bonding pitch is desirable to continuously improve EEP, interconnect density, data bandwidth and system form factor in 3D chiplets integration. There are many factors affecting the SoIC chip-on-wafer bonding quality, such as chip size, chip thickness, process thermal budget, metal density, warpage control, wafer dicing quality, surface treatment conditions, bond tool accuracy and particle control. Insightful understanding of advanced node wafer, process tools, materials, design enablement and good process control are essential to achieve 3D ultra-fine pitch SoIC bond with high yield and high reliability.In this paper, we present for the first time a 3um bond pitch, face-to-face, chip-on-wafer SoIC integration study with low thermal budget. Test vehicle chips in this study are 6 x 6 mm2 in size, with full array interconnects. Daisy chains and Kelvin structure are built-in for chip level leakage test and resistance measurement. Electrical yield validation by wafer acceptance test (WAT) is used for process stability check. EEP analysis, Cu compressive stress prediction and chip level reliability test are also addressed in this study.