Implementation of a 16-channel Sorting Module

Abstract

This paper will present experimental details of a sorting module demonstration system. The sorting module which is currently under construction is shown as a functional schematic in figure 1. Figure 2 is a photograph of the optics. The system implements the bitonic sort based on Batcher’s algorithm implemented with a perfect shuffle. A re-circulating rather than pipelined arrangement is used to minimise hardware requirements to 2 smart pixel chips; • a sorting node array (self-routing exchange/bypass nodes), and • shift register array which acts as the input/output interface.