D. Realey, J. Mankowski, S. Holt, J. Walter, J. Dickens
{"title":"Testing of a low inductance stacked mosfet switch for Pulsed Ring Down Sources","authors":"D. Realey, J. Mankowski, S. Holt, J. Walter, J. Dickens","doi":"10.1109/PPC.2011.6191656","DOIUrl":null,"url":null,"abstract":"An inexpensive and mobile array of Pulsed Ring Down Sources (PRDS) were required to verify previous simulation results. Initial attempts to use a stacked MosFET circuit as a closing switch were unsuccessful due to the additional series inductance of the MosFET stack lowering the frequency of the oscillation on the coaxial radiator. Experimental results showed that by reducing the parasitic inductance due to the geometry of the MosFET stack, the frequency of the oscillation could be increased. Increased series resistance due to the stacked MosFETs was also a concern. In order to minimize the parasitic inductance of the stack and allow for multiple stacks to be connected in parallel, a printed circuit board was designed. Results from testing of the original switch stacks and board assembly are presented and compared with PSPICE simulations. Using the simulation results, the reduction in parasitic inductance can be estimated.","PeriodicalId":331835,"journal":{"name":"2011 IEEE Pulsed Power Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Pulsed Power Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PPC.2011.6191656","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
An inexpensive and mobile array of Pulsed Ring Down Sources (PRDS) were required to verify previous simulation results. Initial attempts to use a stacked MosFET circuit as a closing switch were unsuccessful due to the additional series inductance of the MosFET stack lowering the frequency of the oscillation on the coaxial radiator. Experimental results showed that by reducing the parasitic inductance due to the geometry of the MosFET stack, the frequency of the oscillation could be increased. Increased series resistance due to the stacked MosFETs was also a concern. In order to minimize the parasitic inductance of the stack and allow for multiple stacks to be connected in parallel, a printed circuit board was designed. Results from testing of the original switch stacks and board assembly are presented and compared with PSPICE simulations. Using the simulation results, the reduction in parasitic inductance can be estimated.