An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions

Abstract

The demand for light-weight and high-speed super resolution (SR) techniques is growing because super high-resolution displays, such as 4K/8K ultra high definition televisions (UHDTVs), have become common. We here propose an SR method using over up-sampling and anti-aliasing where no iteration process is required — unlike with conventional SR methods. Our method is able to attenuate jaggies in the edge of an enlarged image and does not need to preserve the entire enlarged image. Therefore, this method is suitable for hardware implementation, and the architecture requires five line buffers only (in the memory section). We implemented the proposed method on a field programmable gate array (FPGA) and demonstrated HDTV-to-4K and-8K SR processing in real time (60 frames per second).