{"title":"A 2-D numerical study of microscale phase change material thermal storage for GaN transistor thermal management","authors":"Xudong Tang, R. Bonner, T. Desai, A. Fan","doi":"10.1109/STHERM.2011.5767174","DOIUrl":null,"url":null,"abstract":"A novel thermal management technology was explored to lower the peak temperature associated with high power GaN transistors in pulse application. The technology involves the use of an embedded microscale PCM heat storage device within the chip (near the active channels of the GaN device), which effectively increases the heat capacity of the material by taking advantage of the latent heat of the PCM. In this study, 2-D transient thermal models were developed to characterize the thermal behavior of GaN transistors with micro-scale PCM heat storage device. The model is capable of computing the spatial-temporal temperature distribution of the GaN transistor as it is rapidly pulsed and captures the formation and evolution of hot spots that form within the device. The model also captures the PCM melting behavior and latent heat absorption during the transient. The use of a PCM can effectively control the hot spot temperature by absorbing a significant portion of the transient heat input. As shown in this modeling study, the use of PCM heat storage in GaN transistors reduces the GaN hot spot temperature for a given heat input. Alternatively, the maximum allowable GaN heat input can be increased with the use of PCM. At a given heat input flux of 5×105 W/cm2, for example, the use of PCM heat storage can lower the peak temperature by 21∼22°C, relative to transistors without PCM (baseline), regardless of the duty cycle ratio. In addition, a transistor with PCM heat storage can accommodate much higher joule heat generation without exceeding the maximum allowable temperature limit, 180°C. In this study, the modeling results show that by integrating a PCM that has a 140°C melting point in a 5μm×6μm groove configuration, the critical heat flux can be increased from 13.34×105 W/cm2 (baseline) to 16.8×105 W/cm2 (with PCM), a 26% improvement. Key PCM design parameters were identified in this modeling study: (1) PCM amount; (2) PCM melting point; and (3) PCM groove structure. Their coupling and the impact on design optimization require further investigation.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"187 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/STHERM.2011.5767174","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A novel thermal management technology was explored to lower the peak temperature associated with high power GaN transistors in pulse application. The technology involves the use of an embedded microscale PCM heat storage device within the chip (near the active channels of the GaN device), which effectively increases the heat capacity of the material by taking advantage of the latent heat of the PCM. In this study, 2-D transient thermal models were developed to characterize the thermal behavior of GaN transistors with micro-scale PCM heat storage device. The model is capable of computing the spatial-temporal temperature distribution of the GaN transistor as it is rapidly pulsed and captures the formation and evolution of hot spots that form within the device. The model also captures the PCM melting behavior and latent heat absorption during the transient. The use of a PCM can effectively control the hot spot temperature by absorbing a significant portion of the transient heat input. As shown in this modeling study, the use of PCM heat storage in GaN transistors reduces the GaN hot spot temperature for a given heat input. Alternatively, the maximum allowable GaN heat input can be increased with the use of PCM. At a given heat input flux of 5×105 W/cm2, for example, the use of PCM heat storage can lower the peak temperature by 21∼22°C, relative to transistors without PCM (baseline), regardless of the duty cycle ratio. In addition, a transistor with PCM heat storage can accommodate much higher joule heat generation without exceeding the maximum allowable temperature limit, 180°C. In this study, the modeling results show that by integrating a PCM that has a 140°C melting point in a 5μm×6μm groove configuration, the critical heat flux can be increased from 13.34×105 W/cm2 (baseline) to 16.8×105 W/cm2 (with PCM), a 26% improvement. Key PCM design parameters were identified in this modeling study: (1) PCM amount; (2) PCM melting point; and (3) PCM groove structure. Their coupling and the impact on design optimization require further investigation.