Hardware design and optimal ADC resolution for uplink massive MIMO systems

Daniel Verenzuela, Emil Björnson, M. Matthaiou
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引用次数: 31

Abstract

This work focuses on the hardware design for the efficient operation of Massive multiple-input multiple-output (MIMO) systems. A closed-form uplink achievable data rate expression is derived considering imperfect channel state information (CSI) and hardware impairments. We formulate an optimization problem to maximize the sum data rate subject to a constraint on the total power consumption. A general power consumption model accounting for the level of hardware impairments is utilized. The optimization variables are the number of base station (BS) antennas and the level of impairments per BS antenna. The resolution of the analog-to-digital converter (ADC) is a primary source of such impairments. The results show the trade-off between the number of BS antennas and the level of hardware impairments, which is important for practical hardware design. Moreover, the maximum power consumption can be tuned to achieve maximum energy efficiency (EE). Numerical results suggest that the optimal level of hardware impairments yields ADCs of 4 to 5 quantization bits.
上行大规模MIMO系统的硬件设计和最佳ADC分辨率
本文主要研究大规模多输入多输出(MIMO)系统高效运行的硬件设计。在考虑不完全信道状态信息和硬件缺陷的情况下,导出了一种闭式上行可实现数据速率表达式。我们提出了一个优化问题,以最大限度地提高总数据速率受制于总功耗的约束。使用了考虑硬件损害水平的一般功耗模型。优化变量为基站(BS)天线数量和每个BS天线的损伤水平。模数转换器(ADC)的分辨率是这种缺陷的主要来源。结果表明,BS天线数量与硬件损伤水平之间的权衡对实际硬件设计具有重要意义。此外,可以调整最大功耗以实现最大能源效率(EE)。数值结果表明,硬件损伤的最佳水平产生4到5个量化比特的adc。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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