Symbol Data Organization in a WB-CDMA Modem

Abstract

For a System-on-Chip (SoC) implementation of mass market devices like a wireless modem user equipment it is crucial -in addition to fulfilling the standardized functional requirements -to optimize both silicon die size and power dissipation. In current VLSI technologies at 65 nm and beneath, beside an optimized logic implementation, a careful dimensioning of all memories is a must. This applies especially to those synchronous random access memories (SRAM) which have to be built on-die because the data throughput is inevitable high like in the signal processing part of a modem's physical layer. This paper presents as an example for the receive path of a WB-CDMA modem a solution for a low power data organization of the frame-wise buffered symbol-streams in between demodulators and channel decoder. This solution is self-adapting in real time to the permanent changing data rates and volume respectively.