Ishan G. Thakkar, S. V. R. Chittamuru, S. Pasricha
{"title":"A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects","authors":"Ishan G. Thakkar, S. V. R. Chittamuru, S. Pasricha","doi":"10.1145/2947357.2947362","DOIUrl":null,"url":null,"abstract":"Photonic devices fabricated with back-end compatible silicon pho-tonic (BCSP) materials can provide independence from the complex CMOS front-end compatible silicon photonic (FCSP) process, to sig-nificantly enhance photonic network-on-chip (PNoC) architecture performance. In this paper, we present a detailed comparative analy-sis of a number of design tradeoffs for CMOS front-end and back-end compatible devices for silicon photonic interconnects. A cross-layer optimization of multiple device-level and link-level design pa-rameters is performed to enable the design of energy-efficient on-chip photonic interconnects using BCSP devices. The optimized design of BCSP on-chip links renders more energy-efficiency and aggregate bandwidth than FCSP on-chip links, in spite of the inferior opto-elec-tronic properties of BCSP devices. Our experimental analysis com-pares the use of BCSP and FCSP links at the architecture level, and shows that the optimized design of the BCSP-based Firefly PNoC achieves 1.15x greater throughput and 12.4% less energy-per-bit on average than the optimized design of FCSP-based Firefly PNoC. Similarly, the optimized design of the BCSP-based Corona PNoC achieves 3.5x greater throughput and 39.5% less energy-per-bit on average than the optimized design of FCSP-based Corona PNoC.","PeriodicalId":331624,"journal":{"name":"2016 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2947357.2947362","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
Photonic devices fabricated with back-end compatible silicon pho-tonic (BCSP) materials can provide independence from the complex CMOS front-end compatible silicon photonic (FCSP) process, to sig-nificantly enhance photonic network-on-chip (PNoC) architecture performance. In this paper, we present a detailed comparative analy-sis of a number of design tradeoffs for CMOS front-end and back-end compatible devices for silicon photonic interconnects. A cross-layer optimization of multiple device-level and link-level design pa-rameters is performed to enable the design of energy-efficient on-chip photonic interconnects using BCSP devices. The optimized design of BCSP on-chip links renders more energy-efficiency and aggregate bandwidth than FCSP on-chip links, in spite of the inferior opto-elec-tronic properties of BCSP devices. Our experimental analysis com-pares the use of BCSP and FCSP links at the architecture level, and shows that the optimized design of the BCSP-based Firefly PNoC achieves 1.15x greater throughput and 12.4% less energy-per-bit on average than the optimized design of FCSP-based Firefly PNoC. Similarly, the optimized design of the BCSP-based Corona PNoC achieves 3.5x greater throughput and 39.5% less energy-per-bit on average than the optimized design of FCSP-based Corona PNoC.