A 60 GHz 30.5% PAE Differential Stacked PA with Second Harmonic Control in 45 nm PD-SOI CMOS

Abstract

This paper presents a 60 GHz highly efficient single-stage differential stacked Class AB power amplifier (PA) with second harmonic control. The circuit has been realized in a 45 nm PD-SOI CMOS technology. Measurement results show that the power amplifier achieves a maximum output power ($P_{max}$) of 15.3 dBm with a competitive maximum power-added efficiency ($PAE_{max}$) of 30.5 % at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a 1.8 V supply and the chip core size is 0. 36mmx0.35 mm.