BUCS - a bottom-up cache structure for networked storage servers

Ming Zhang, Qing Yang
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引用次数: 2

Abstract

This paper introduces a new caching structure to improve server performance by minimizing data traffic over the system bus. The idea is to form a bottom-up caching hierarchy in a networked storage server. The bottom level cache is located on an embedded controller that is a combination of a network interface card (NIC) and a storage host bus adapter (HBA). Storage data coming from or going to a network are cached at this bottom level cache and meta-data related to these data are passed to the host for processing. When cached data exceed the capacity of the bottom level cache, some data are moved to the host RAM that is usually larger than the bottom level cache. This new cache hierarchy is referred to as bottom-up cache structure (BUGS) in contrast to a traditional CPU-centric top-down cache where the top-level cache is the smallest and fastest, and the lower in the hierarchy the larger and slower the cache. Such data caching at the controller level dramatically reduces bus traffic and leads to great performance improvement for networked storages. We have implemented a proof-of-concept prototype using Intel's IQ80310 reference board and Linux network block device. Through performance measurements on the prototype implementation, we observed up to 3 times performance improvement of BUCS over traditional systems in terms of response time and system throughput.
BUCS——用于网络存储服务器的自下而上的缓存结构
本文介绍了一种新的缓存结构,通过最小化系统总线上的数据流量来提高服务器性能。其思想是在网络存储服务器中形成自下而上的缓存层次结构。底层缓存位于嵌入式控制器上,该控制器是网络接口卡(NIC)和存储主机总线适配器(HBA)的组合。来自网络或前往网络的存储数据被缓存在这个底层缓存中,与这些数据相关的元数据被传递给主机进行处理。当缓存的数据超过底层缓存的容量时,一些数据被移动到通常比底层缓存大的主机RAM中。这种新的缓存层次结构被称为自底向上缓存结构(BUGS),与传统的以cpu为中心的自顶向下缓存形成对比,在自顶向下缓存中,顶层缓存最小、最快,层次结构越低,缓存越大、速度越慢。这种控制器级的数据缓存可以显著减少总线流量,并极大地提高网络存储的性能。我们已经使用英特尔的IQ80310参考板和Linux网络块设备实现了一个概念验证原型。通过对原型实现的性能测量,我们观察到在响应时间和系统吞吐量方面,BUCS的性能比传统系统提高了3倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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