A NUMA-Aware Fine Grain Parallelization Framework for Multi-core Architecture

Abstract

We present some solutions to handle two problems commonly encountered when dealing with fine grain parallelization on multi-core architecture: Expressing algorithms using a task grain size suitable for the hardware and minimizing the time penalty due to Non Uniform Memory Accesses. To evaluate the benefit of our work we present some experiments on the fine grain parallelization of an iterative solver for sparse linear systems with some comparisons with the Intel TBB approach.