20 nm FDSOI process and design platforms for high performance/ low power systems on chip

Abstract

The race towards further density increase in CMOS circuit integration is entering a new era where choices are needed for the device shrink. Beyond 20nm, a consensus says that MOSFETs will go fully depleted. They can either be 2D or 3D, i.e. 2D fully depleted silicon films on Oxide (FDSOI) or 3D with fully depleted silicon fins. We believe that FDSOI films allow continuing smoothly Moore's Law without introducing drastic design disruptive steps. We have developed FDSOI Process and Design Platforms that are in the shrink trend from previous generations. Moreover, since FDSOI devices are compatible with the Bulk design rules and constraints, it becomes possible, within the same technology node, to hit the performance boost usually targeted with the next one. This has become of utmost importance today where the introduction of a new node gets complex and costly because of the delay to get appropriate advanced Lithography tools. In this presentation, we review the challenges for the 20nm FDSOI nodes by looking at performance, power and process complexity.