Analog circuit performance of high mobility ultrathin-body InAsSb-on-insulator MOSFETs

Abstract

In this paper, we report, for the first time, device parameters related to analog circuit applications of symmetric double gate InAsSb channel n-MOSFETs. Our model is based on the carrier concentration and the Pao-Sah's current formulation considering field dependent electron mobility and interface trapped-charge-density. Accuracy of the model has been verified by comparing analytical results with the reported experimental data. The proposed model has been employed to calculate the drain current of DG MOSFETs for different gate and drain voltages and also to compute various analog performance metrics such as transconductance, output conductance, transconductance efficiency, voltage gain and cut-off frequency for a wide range of bias conditions and interface trap charge densities. Our results reveal that InAsSb devices outperform their equally sized Si counterpart for analog circuit applications.